1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and in particular, to a structure of a p-n junction and a manufacturing method of the same.
2. Description of the Background Art
A structure of a conventional n-channel transistor will be described below with reference to the drawings.
FIG. 12 is a cross section schematically showing a conventional n-channel transistor. Referring to FIG. 12, element separating oxide films 113 are formed in a surface of a p-type silicon substrate 103 in element separating regions 160. The element separating oxide films 113 separate and define an element forming region 150 on the p-type silicon substrate 103. An n-channel transistor is formed on the element forming region 150.
The n-channel transistor includes a pair of source/drain diffusion regions 111, a gate oxide film 115 and a gate electrode 117. The pair of source/drain diffusion regions 111 are formed on the surface of the p-type silicon substrate 103 with a predetermined space between each other. Each of the source/drain diffusion regions 111 has a double structure formed of an n.sup.- impurity diffusion region 107 and an n.sup.+ impurity diffusion region 109, and thus has an LDD (lightly doped drain) structure. Owing to the LDD structure of the source/drain diffusion region 111, the intensity of electric field in a channel direction near the drain region is reduced, and thus the generation of hot electrons is suppressed. The source/drain diffusion regions 111 are adjacent to the element separating oxide films 113. The gate electrode 117 is formed on the region between the pair of source/drain diffusion regions 111 with the gate oxide film 115 therebetween. Side surfaces of the gate electrode 117 are covered with side walls 119.
A p-type impurity diffusion region 105 is formed in the p-type silicon substrate 103. In the element separating regions 160, the p-type impurity diffusion region 105 is adjacent to lower surfaces of the separating oxide films 113, and in the element forming region 150, it is located near the under side of the n-channel transistor. The concentration of p-type impurity in the p-type impurity diffusion region 105 is larger than that in the p-type silicon substrate 103. The p-type impurity diffusion region 105 has a peak of concentration of impurity represented by dotted line 105a. The p-type impurity diffusion region 105 has portions, which are located near the lower ends of the element separating oxide films 113 and are substantially in contact with the n.sup.+ impurity diffusion regions 109. The p-type impurity diffusion region 105 and element separating oxide films 113 serve to electrically separate the n-channel transistor from other elements.
The concentration of impurity in the p-type silicon substrate 103 is 10.sup.15 cm.sup.-3. The concentration of impurity in the p-type impurity diffusion region 105 is between 10.sup.17 and 10.sup.18 cm.sup.-3. The concentration of impurity in the n.sup.- impurity diffusion region 107 is between 10.sup.17 and 10.sup.18 cm.sup.-3. The concentration of impurity in the n.sup.+ impurity diffusion region 109 is approximate, but does not exceed 10.sup.20 cm.sup.-3.
Now, a manufacturing method of the n-channel transistor shown in FIG. 12 will be described below.
FIGS. 13-20 are schematic cross sections showing steps in the manufacturing method of the n-channel transistor in the prior art.
Referring to FIG. 13, a thin silicon oxide film 121 is formed on the whole surface of the p-type silicon substrate 103. A silicon nitride film 123 is formed on the whole surface of the thin silicon oxide film 121.
Referring to FIG. 14, a photoresist 125 is applied to the whole surface of the silicon nitride film 123. The photoresist 125 is patterned, e.g., by an exposure processing. Using the patterned photoresist 125 as a mask, the silicon nitride film 123 is patterned.
Referring to FIG. 15, the photoresist 125 is removed. Using the silicon nitride film 123 as a mask, portions not covered with the silicon nitride film 123 are selectively oxidized, so that the separating oxide films 113 are formed in the surface of the p-type silicon substrate 103.
Referring to FIG. 16, the thin silicon oxide film 121 and the silicon nitride film 123 located in the element forming region of the p-type silicon substrate 103 are sequentially etched. Thereafter, boron (B) is ion-implanted into the whole surface of the p-type silicon substrate 103. This implantation forms the p-type impurity diffusion region 105 in the p-type silicon substrate 103. In the element separating regions, the p-type impurity diffusion region 105 is located near the lower surfaces of the element oxide films 113, and in the element forming region, it is located at a predetermined depth from the surface of the p-type silicon substrate 103. The concentration of impurity in the p-type impurity diffusion region 105 is higher than that in the p-type silicon substrate 103.
Referring to FIG. 17, the thin silicon oxide film 115 is formed on the exposed surface of the p-type silicon substrate 103, e.g., by thermal oxidation. The polysilicon layer 117 is formed on the whole surface of the silicon substrate 103.
Referring to FIG. 18, the thin silicon oxide film 115 and polysilicon layer 117 are sequentially patterned, e.g., by the photolithography or RIE method. Thereby, the gate electrode 117 and gate oxide film 115 are formed. Using the gate electrode 117 and element separating oxide films 113 as a mask, phosphorus (P) is ion-implanted into the whole surface of the silicon substrate 103. This implantation forms the pair of n.sup.- impurity diffusion regions 107, which are located at opposite sides of a region under the gate electrode 117, on the surface of the p-type silicon substrate 103.
Referring to FIG. 19, a silicon oxide film 119 is formed on the whole surface of the p-type silicon substrate 103. Anisotropic etching is applied to the silicon oxide film 119, whereby the side walls 119 covering the side surfaces of the gate electrode 117 are formed.
Referring to FIG. 20, the side walls 119, gate electrode 117 and element separating oxide films 113 are used as a mask for ion implantation of arsenic (As) into the whole surface of the p-type silicon substrate 103. This implantation forms the pair of n.sup.+ impurity diffusion regions 109, which are located at opposite sides of a region under the gate electrode 117 and side walls 119. The n.sup.+ impurity diffusion layers 109 and n.sup.- impurity diffusion layers 107 form the source/drain diffusion regions 111 having the LDD structure.
In the description, "n.sup.+ " indicates that the n-type impurity is contained at a relatively high concentration, and "n.sup.- " indicates that the n-type impurity is contained at a relatively low concentration.
The conventional n-channel transistor has the structure and is formed as described above.
Integration of elements to a higher extent inevitably requires miniaturization of the elements. This also requires the miniaturization of the element separating oxide films which electrically separate the elements from each other. More specifically, a length L and a thickness W of the element separating oxide film 113 shown in FIG. 12 are reduced. The reduction of sizes of the element separating oxide film may impair the effect for electrically separating the elements from each other. For this reason, the p-type impurity diffusion region 105 is formed in order to increase the effect for electrically separating the elements from each other. The portions of the p-type impurity diffusion region 105 located in the element separating regions 160 serve mainly as a channel cut layer for preventing generation of an inversion layer at an interface between the insulator and semiconductor. The portion of the p-type impurity diffusion region 105 located in the element forming region 150 has functions including suppression of a latch-up phenomenon, e.g., in a complementary MOS (metal oxide semiconductor) transistor. In the latch-up phenomenon, current flows from a power supply terminal (V.sub.DD) to a ground terminal in an IC (integrated circuit) of the complementary MOSs without interruption. As described above, the p-type impurity diffusion region 105 is provided for the electrical separation of the elements in order to comply with the high integration of the elements.
However, the integration to a further extent requires further increase of the electrically separating effect. In order to satisfy this requirement in the n-channel transistor shown in FIG. 12, the concentration of the p-type impurity in the p-type impurity diffusion region 105 must be increased.
Meanwhile, the miniaturization of elements also requires improvement of the current driving capacity of the elements. In order to improve the current driving capacity in the n-channel transistor shown in FIG. 12, the concentration of n-type impurity in the source/drain regions must be increased. As described above, the concentration of p-type impurity in the p-type impurity diffusion region 105 and the concentration of n-type impurity in the n.sup.+ impurity diffusion region 109 must be high in view of the further integration.
FIG. 21A shows change of carrier concentration at positions along line C.sub.1 -D.sub.1 in FIG. 12. FIG. 21B shows change of carrier concentration at positions along line C.sub.2 -D.sub.2 in FIG. 12.
Referring to FIG. 12 and FIGS. 21A and 21B, the concentrations of impurity in the p-type impurity diffusion region 105 and n.sup.+ impurity diffusion region 109 have large values in view of the further integration. As the impurity concentrations increase, the carrier concentrations also increase. In this case, a p-type impurity region and an n-type impurity region, each of which has a high carrier concentration, are adjacent to each other at a location near the p-n junction formed at the region between the p-type impurity diffusion region 105 and n.sup.+ impurity diffusion region 109. In the p-n junction, the p-type and n-type carriers cancel each other, so that a region without a carrier, a depletion layer is formed. In the case where the p-type and n-type impurity regions having high carrier concentrations are adjacent to each other, the concentration of n-type carrier at a position between the depletion layer of the p-n junction and the n.sup.+ impurity diffusion layer 109 rapidly increases in accordance with increase of the distance from the depletion layer. Meanwhile, the concentration of p-type carrier at a position between the depletion layer of the p-n junction and the p-type impurity diffusion layer 105 rapidly increases in accordance with increase of the distance from the depletion layer. Therefore, gradients of concentrations of p-type and n-type carriers near the p-n junction are large. The gradient of concentration of carrier is equal to a rate of change of the carrier concentration with respect to a displacement of the position, and is represented by the inclination of alternate long and short dash line n.sub.3 --n.sub.3 or n.sub.4 --n.sub.4, or alternate long and two short dashes line p.sub.3 --p.sub.3 or p.sub.4 --p.sub.4.If the gradient of the carrier concentration is large, the absolute value of the inclination, e.g., of alternate long and short dash line n.sub.3 --n.sub.3 is large.
FIGS. 21A and 21B do not show the concentrations of carriers at and near the surface of the p-type silicon substrate 103, and show the concentrations of carriers only at regions designated by alternate long and short dash line C.sub.1 -D.sub.1 and C.sub.2 -D.sub.2 in FIG. 12. In FIGS. 21A and 21B, the depletion layer formed at the p-n junction is eliminated for simplicity reason.
As described above, in the case where the impurity concentration at the p-type impurity diffusion region 105 and n.sup.+ impurity diffusion region 109 are increased in view of the high integration, the gradients of concentrations of carriers near the p-n junctions increase, which results in the following disadvantage.
FIGS. 22A and 22B schematically show a section of a portion corresponding to a region R encircled with alternate long and two short dashes line in FIG. 12, and show results of simulation relating to concentration of the electrical field. FIG. 22A shows the result in the case where the source/drain regions are formed by single ion-implantation of arsenic (As), and FIG. 22B shows the result in the case where the source/drain regions are formed by double ion-implantation of phosphorus (P). Conditions for the simulation are that the concentration of n-type impurity in the source/drain region 211 is 10.sup.20 cm.sup.-3, the concentration of impurity in the p-type silicon substrate 203 is 10.sup.17 cm.sup.-3, and the concentration of impurity in the p-type impurity diffusion region 205 is 10.sup.18 cm.sup.-3. A reverse bias potential of 9 V is applied to the p-n junction formed between the source/drain region 211 and the p-type silicon substrate 203 or p-type impurity diffusion region 205. In the figure, dotted lines 231, 232 and 233 are contour lines of the field intensities of 0.8.times.10.sup.6 V/cm, 1.0.times.10.sup.6 V/cm and 1.2.times.10.sup.6 V/cm, respectively. From the results of simulation, it has been found that a high field generates along the p-n junction in the case where the n-type and p-type impurity regions of the high concentrations are adjacent to each other. In particular, it has been found that a higher field generates at the p-n junction in which a relative distance between the n-type impurity region (source/drain region) and the p-type impurity region of the high concentrations is small.
For the above reason, it can be estimated that a higher field generates along the p-n junction formed between the p-type impurity diffusion region 105 and n.sup.+ impurity diffusion region 109 shown in FIG. 12 if the concentration of carriers of these regions 105 and 109 are further increased.
Meanwhile, the gradients of carrier concentrations near the p-n junction are large, as shown in FIGS. 21A and 21B, so that a diffusion current is liable to generate near the p-n junction.
FIG. 23 is a diagram for showing that the diffusion current is liable to generate if the gradient of concentration of carrier is large. Referring to FIG. 23, the abscissa indicates the concentration of carrier, and the ordinate indicates the spatial position. In general, the carrier has the tendency that it moves from a region of a high concentration carrier to a region of a lower concentration. In the case of curve t.sub.1 representing the high gradient of carrier concentration, the carrier is liable to move to a peripheral region of the low carrier concentration. If the carrier in the state represented by the curve t.sub.1 moves to the peripheral region of the low carrier concentration, the concentration of carrier with respect to the position attains the state represented by the curve t.sub.2, and further changes to the state represented by the curvature t.sub.3. Thus, the state of the concentration of carrier changes to the state of the small gradient of the lower carrier concentration. The carrier moves owing to the diffusion, as described above. Since the carrier has an electric charge, the movement of carrier generates the diffusion current. The diffusion current generates to a higher extent in accordance with increase of the gradient of carrier concentration, as described above.
For the foregoing reason, in the case of the large gradient of concentration of carrier near the p-n junction in the region between the p-type impurity diffusion region 105 and n.sup.+ impurity diffusion region 109, it is estimated that a high electric field generates at the p-n junction if a reverse bias potential is applied, and that the diffusion current is liable to generate. Therefore, application of the reverse bias potential to the p-n junction causes such a disadvantage that the leak current is liable to generate at the p-n junction due to actions of the high field and diffusion current.
The leak current may be caused also by a reason other than the foregoing. Referring to FIG. 12, defect is introduced into side edges of the element separating oxide films 113 during the formation of the element separating oxide films 113. If the defect distributes in the depletion layer during the operation of the element, the current leaks from the defect, i.e., the leak current generates. However, the leak current caused by the defect can be prevented in a semiconductor device disclosed in the Japanese Patent Laying-Open No. 2-133929 (1990).
The semiconductor device disclosed in this publication is shown in FIG. 24. FIG. 24 is a schematic cross section of the semiconductor device disclosed in this publication. Referring to FIG. 24, field insulating films 313 are selectively formed on a silicon substrate 303. At the vicinity of the under surfaces of the field insulating films 313, p.sup.+ channel cut layers 305 are formed in the p-type silicon substrate 303. The field insulating films 313 and p.sup.+ channel cut layers 305 separate and define an element forming region, in which a MOS transistor is formed.
The MOS transistor includes a pair of source and drain regions 301, 307 and 309, a gate insulating film 315 and a gate electrode 317. The pair of source and drain regions 301, 307 and 309, which form the LDD structure, are formed on the p-type silicon substrate 303. The gate electrode 317 is formed on the surface of the region located between the pair of source and drain regions with the gate insulating film 315 therebetween.
According to the structure of the semiconductor device shown in the foregoing publication, the source/drain regions include the regions 301 which extend along and contact with the side edges of the field insulating films 313. Owing to the provision of the n-type source and drain regions 301, the crystal defect, which was introduced into the p-type silicon substrates 303 during the formation of the field insulating films 313, is contained in the n-type source and drain regions 301. Therefore, the crystal defect introduced into the side edges of the field insulating films 313 does not distribute into depletion layers during the operation of the MOS transistor, so that junction leak is prevented and element characteristics are improved.
The above matter is disclosed in the foregoing publication.